1. Technical Field
Embodiments of the invention relate generally to a method for measuring overlay and use of an overlay mark. More particularly, the embodiments relate to an overlay measuring method adapted to calculate overlay data through the measurement of overlay upon implementing on a wafer an initial photolithography, and an overlay mark for use in the method.
2. Discussion of Related Art
The manufacture of semiconductor devices involves a complex sequence of individual fabrication processes. The overall complexity of this manufacturing sequence and the competitive nature of the semiconductor industry generally result in stringent demands being placed upon the accuracy of each constituent fabrication process. That is, commercial competitiveness demands high product yield, and high product yield demands great accuracy in the individual fabrication processes. As a result, methods and apparatuses adapted to detect, identify and measure process errors for each constituent fabrication process in the manufacturing sequence have been the subject of active study and refinement. Various photolithography processes are commonly included in the sequence of fabrication processes used to manufacture semiconductor devices. Photolithography processes are notoriously susceptible to changes in process conditions, e.g., temperature, humidity, mechanical vibrations induced by preceding processes, etc. Thus, numerous corrective methods and devices have been proposed to mitigate the effects of process condition variations in relation to photolithography processes.
One common problem associated with the accurate performance of a photolithographic process is the misalignment of a photoresist pattern. Photoresist patterns are commonly used to define circuit patterns on a semiconductor substrate.
Generally speaking a photoresist pattern is formed by a photolithographic process comprising several distinct steps including a coating process, an alignment and exposure process, a development process, and an overlay measurement. The coating process is usually performed by spinner. A stepper is typically used to first expose a photoresist layer to a patterned light source having a particular wavelength and then develop the exposed material layer. A scanner or a scanning electron spectroscopy apparatus are then used to perform the overlay measurement process.
As semiconductor devices become more highly integrated on ever larger wafers—thereby reducing design tolerances—and as the number of individual photolithography processes involved in the manufacture of a semiconductor device rises, the importance of alignment accuracy for the photoresist patterns in the various photolithography processes only increases. To prevent defects in the semiconductor device arising from misalignment, it is essential to verify with exceptional accuracy (e.g., optimized accuracy), the alignment of a photoresist pattern formed on a wafer being processed.
Conventional methods directed to the optimization of a overlay measurement are disclosed, for examples, in U.S. Pat. Nos. 5,696,835 and 6,357,131.
The conventional methods of overlay measurement generally include, first, forming a photoresist pattern (e.g., an alignment measurement pattern) on a wafer, and then measuring an overlapped position between the photoresist pattern and an underlying pattern layer (e.g., a reference pattern). Unfortunately, contemporary circuit patterns defined by the various pattern layers are so complex that a global overlap examination in not practical. Thus, special overlay marks are strategically incorporated within the pattern layers to indicate via sampled examination the state of pattern overlay. Overlay marks are often formed in relation to a scribe line near the outer edge of the area on the wafer in which the circuit pattern is formed.
Conventional overlay measurements are conducted in accordance with a defined number of exposure “shots” applied to a wafer, or the overall size of the wafer. Overlay measurements are made in relation to overlay and alignment marks on a global rather than local basis relative to the entire surface area of the wafer being processed.
Overlay data is conventionally obtained using a regression analysis for each overlay measurement taken with respect to an overlay mark formed on the wafer. The overlay data indicates degree(s) of distortion and/or rotation in the X and Y directions between the wafer and an optical reticle or mask defining the pattern light exposing the photoresist layer. For example, the deviations from ideal of the overlay measurement data may be classified into wafer related parameters and reticle related parameters. Wafer related parameter are generally related to positional errors that vary between individual shots due, for example, to poor stamping in reference to the center of the wafer. Reticle related parameters are generally related to maladjustments or omission of particular component(s) in the exposure device associated with the reticle. The resulting variations in magnification and/or focus of the exposing light through the reticle ultimately result in pattern errors.
The conventional overlay measurement device seeks to calculate correction factors using the overlay data to thus provide feedback to the exposure device in hopes of preventing defects due to misalignment of pattern layers on the wafer being processed. Unfortunately, the conventional overlay measurement method and related apparatus suffer from several problems.
For example, the conventional overlay measurement method (e.g., one obtaining overlay data through the use of regression analysis applied to each overlay measurement applied to overlay marks formed on the wafer) suffers from yield rate problems due to the absence of overlay measurement data related to a first layer or a photoresist pattern (active layer) formed on the wafer in an initial state where an underlying pattern layer is yet to exist.